1. Field of the Invention
This invention relates to a method and apparatus for overlay alignment measurement during various stages of integrated circuit processing for microelectronic fabrication.
2. Description of Related Art Including Information Disclosed Under 37 CFR 1.97 and 1.98
Planar technology that is conventionally used in high volume production of integrated circuits used in computers, communication equipment, cellular phones and other consumer electronic devices, relies on successive processing of materials deposited in the form of thin films on top of silicon or other substrates. If two successive layers are misaligned with respect to each other, the device performance degrades and it may fail. For example, without any limitations, a misalignment can lead to an increase in the resistance of via's and contacts and hence an increase in the RC time delay of the circuit, leading to a reduction in the operable speed of the device. It is of great interest to measure the alignment accuracy of one layer's placement or registration with respect to a preceding layer's position with high precision and repeatability and with good matching between metrology tools. “Perfect alignment” rarely happens; every integrated circuit design allows for some misalignment between two succeeding layers; it is of great importance to know how well two layers are aligned with regard to each other and to know whether or not the “misalignment” is outside a prescribed tolerance band. Overlay error is the mis-registration in placement of a layer above a previously processed layer. As used herein “overlay error” or “alignment error” is defined as the deviation from perfect alignment in the x and the y direction as noted by Δx or Δy; when rotational misalignment is present, Δx or Δy is a function of the exact location of the measurement.
Overlay error measurement is normally done with specially designed targets (or marks) placed at pre-selected locations on the wafer. These targets are typically several tens of microns large and fit within the scribe or kerf area between rows and columns of die. Traditionally overlay targets consisted of box-in-box or bar-in-bar structures. However, recently, grating-based overlay metrology techniques have emerged which require targets periodic in nature. These gratings can be one-dimensional (i.e. rows of lines) or two-dimensional, for example, rows or columns of squares, rectangles, triangles, parallelograms, circles, trapezoids or any other shape that is lithographically printable. U.S. Pat. No. 6,985,618 describes a wide variety of overlay targets. Typically, a grating is placed on the previous layer and another grating on the current layer that is being processed. Normally a grating placed on a previous layer is fully processed (i.e. etched or filled, etc.) and the grating on the current layer is in a photo-resist layer. An overlay metrology tool measures a deviation in placement of a grating in a photo-resist layer with respect to a grating in the processed layer. “Overlay error” is defined as the deviation from ideal, rotational and translational, of the layer being processed to a layer previously processed.
In an overlay metrology tool described in U.S. Pat. No. 6,023,338, issued to Bareket, the system requires mechanical scanning of a focused spot on the gratings. In U.S. Pat. No. 6,710,876, issued to Nikoonahad et al, optical phase of the first order diffracted beams is used to extract the overlay error. In U.S. Pat. No. 7,009,704 issued to Nikoonahad et al the overlay target is imaged with a CCD using a mid numerical aperture (NA) lens and the shift between the adjacent gratings are computed by software. Mechanical systems suffer from wear and tear, friction, instability and drift over time leading to unreliable overlay error measurement. With reference to the optical phase techniques as described in U.S. Pat. No. 6,710,876, the information content in the first diffracted orders is insufficient and it does not adequately address the overlay measurement needs. Also, measuring the optical phase from first order diffraction alone suffers from complications in separating large phase shift arising from the height of the resist layer and the periodic phase shifts embedded in the phase of the reflection coefficient of the previously processed layer. The use of linear mechanical translation of a Wallaston prism or the use of an acousto-optic deflector has been proposed but these add to the complexity of the system. The overlay error control necessary for sub-100 nm integrated circuit devices is less than about five percent of the minimum feature size with a 3σ precision of less than one percent. This resolution is certainly below the imaging capability of any optical imaging system and, as a result, current imaging systems, as described in 7,009,704, resort to a significant amount of algorithmic post processing to attain meaningful overlay information. None of the techniques described above are fully satisfactory. Clearly additional sensitivity to “overlay-only” errors is of great value. It is, therefore, desirable to develop a system with better performance and a simpler characteristic.